(1) Technical Field
This invention generally relates to electronic circuits, and more specifically to field effect transistor structures.
(2) Background
A field effect transistor (FET) employs a gate-modulated conductive channel between a source region and a drain region. Various types of FETs exist, including insulated gate FETs (IGFETs), of which the most common type are metal-oxide-semiconductor FETs (MOSFETs). MOSFETs having n-type or p-type channel conductivity are referred to as an “NMOSFET” or “PMOSFET”, respectively.
FIG. 1 is a schematic diagram of a conventional prior art FET 100 with an optional body diode. Shown are the source S, drain D, and gate G. Also shown is body connection B to the body or substrate on which the FET is fabricated. As is well known, when a voltage is applied between the gate G and source S terminals of a FET, a generated electric field penetrates through the gate oxide to the transistor body B. As one example, for an enhancement mode MOSFET device, a positive bias voltage applied to the gate G creates a conductive channel in the channel region of the MOSFET body through which current passes between the source S and drain D. As another example, for a depletion mode MOSFET device, a conductive channel is present with a zero bias voltage applied to the gate G; varying the voltage applied to the gate G modulates the conductivity of the channel and thereby controls the current flow between the source S and drain D. Note that while the amount of current flow may be modulated continuously, another common use of a FET is as a simple binary switch having only “ON” and “OFF” states, where a signal either passes through the FET between the drain D and source S (“ON” state) or the signal is blocked (isolated) from passing between the drain D and source S (“OFF” state).
No matter what mode of operation a FET employs (i.e., enhancement mode or depletion mode), under some circumstances for a FET operated as a binary switch, when the FET is switched to an OFF-state with a nonzero gate bias voltage applied with respect to the source S and drain D, an accumulated charge may occur under the gate G. When such a FET is in an OFF-state, and when carriers are present in the channel region having a polarity that is opposite to the polarity of the source and drain carriers, the FET is defined herein as operating in an “accumulated charge regime”.
As described in U.S. Pat. No. 7,910,993 B2, issued Mar. 22, 1011, entitled “Method and Apparatus for use in Improving Linearity of MOSFET'S using an Accumulated Charge Sink” and assigned to the assignee of the present invention, when used in certain circuit implementations, conventional MOSFETs operating in the accumulated charge regime exhibit undesirable non-linear characteristics that adversely impact circuit performance. For example, accumulated charge adversely affects the linearity of OFF-state silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) MOSFETs, and more specifically, accumulated charge adversely affects the linearity of capacitances that contribute to the drain-to-source capacitance (Cds). For such MOSFETs operating in an OFF-state, Cds is referred to as Coff. For bias conditions where the gate bias Vg is provided by a circuit having an impedance that is large compared to the impedances of the contributing capacitances to Coff, such contributing capacitances adversely affect harmonic distortion, intermodulation distortion, and other performance characteristics of such circuits.
SOI and SOS MOSFETs are often used in applications in which operation within the accumulated charge regime adversely affects MOSFET performance. Unless the accumulated charge is removed or otherwise controlled, it detrimentally affects performance of such MOSFETs under certain operating conditions. As described in U.S. Pat. No. 7,910,993 B2 referenced above, one way of controlling or removing accumulated charge in such MOSFET's is by coupling the body B to the gate G through a diode 102, as shown in FIG. 1.
However, while this solution significantly reduces harmonic distortion and intermodulation distortion in MOSFET's, adding the diode 102 does not eliminate harmonic distortion in such devices. Second-order harmonics, for example, adversely affect radio frequency (RF) signals in particular. For example, FIG. 2 is a plot of measurements of second harmonic power versus drain to source voltage Vds for four configurations of prior art RF FETs (configured as a “stack” of one FET, in a shunt configuration OFF state): an even number of gate “fingers” and no body-to-gate diode (plot curve 202); an even number of gate “fingers” and a body-to-gate diode (plot curve 204); an odd number of gate “fingers” and no body-to-gate diode (plot curve 206); and an odd number of gate “fingers” and a body-to-gate diode (plot curve 208). The number of “fingers” refers to physical configurations of the FETs as shown in FIG. 3 and FIG. 4.
FIG. 3 shows a top-down layout view of a first prior art FET 300 in which source 32 and drain 34 regions are interdigitated as shown on a substrate or body 36. An overlying gate layer 38 with an even number of “fingers” (four are shown by way of example) is situated between the interdigitated projections of the source 32 and drain 34 regions. When biased by an appropriate voltage level, the gate layer 38 modulates the conductive channels between the source 32 and drain 34 regions. Also shown is a drain-to-body tie 310, discussed below.
FIG. 4 shows a top-down schematic view of a second prior art FET 400 in which source 402 and drain 404 regions are interdigitated as shown on a substrate or body 406. An overlying gate layer 408 with an odd number of “fingers” (three are shown by way of example) is situated between the interdigitated projections of the source 402 and drain 404 regions. As in FIG. 3, when biased by an appropriate voltage level, the gate layer 408 modulates the conductive channels between the source 402 and drain 404 regions. Also shown is a drain-to-body tie 410, discussed below.
Referring back to FIG. 2, each plot curve 202-208 shows the drain-to-body capacitance Cdb and source-to-body Csb capacitance (impedance) asymmetry for an associated configuration. During normal operation with a FET in an OFF state, Vds=0V DC. It is desirable to have the lowest second harmonic (“2fo”) value at the vertical axis of Vds=0V; in the illustrated example, plot curve 208 has that characteristic at crossing-point 210. The plots of 2fo values across different Vds values show that there exists a value of Vds (effectively an offset voltage) for each FET configuration where the effective capacitances of Cdb and Csb are equivalent (that is, at the nadir of each plot curve). FET devices with an odd number of gate fingers have lower capacitance asymmetry for Csb and Cdb, and accordingly better harmonic characteristics. Thus, the plot curves 206, 208 for devices with an odd number of gate fingers have Vds=0V crossing-points with lower 2fo values than do the plot curves 202, 204 for devices with an even number of gate fingers. However, the use of an odd number of gate fingers does not totally cancel the asymmetry of Csb and Cdb.
More specifically, because of the drain-to-body ties 310, 410 in FIG. 3 and FIG. 4, respectively, for m even fingers, Cdb is proportional to (m−1) times the capacitance of the device junction per finger, plus the capacitance of the drain-body coupling, whereas Csb is proportional to (m−2) times the capacitance of the device junction per finger. Form odd fingers, Cdb is proportional to (m−1) times the capacitance of the device junction per finger, plus the capacitance of the drain-body coupling, whereas Csb is proportional to only (m−1) times the capacitance of the device junction per finger. As should be apparent, even with an odd number of gate fingers, Csb≠Cdb.
The addition of a body-to-gate diode in a FET device improves the suppression of harmonics. Thus, the plot curves 204, 208 for devices with a body-to-gate diode show greater harmonic suppression than do the plot curves 202, 206 for devices without such a diode. However, the addition of a body-to-gate diode does not completely remove the 2nd harmonic. Even the combination of odd gate fingers and a body-to-gate diode (curve 208) does not eliminate the second-order harmonic. Moreover, existing implementations of FET's with a body-to-gate diode can actually cause greater Csb, Cdb asymmetry.
Accordingly, there is a need for a structure and method for reducing second-order harmonic distortion in FETs used in applications, such as RF signals, that are sensitive to such distortion. The present invention addresses that need.